(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for the creation of passive semiconductor components and circuits at one level using selected and non-identical dielectric materials therefore.
(2) Description of the Prior Art
Semiconductor devices are typically created using numerous related processing steps for the creation of device features. After active semiconductor devices have been created, these devices are typically personalized, which can take the form of interconnecting such basic sub-functions as gate arrays or DRAM cells or the interconnecting of logic functions to create a more complex device.
In addition to creating active semiconductor devices, such as MOSFET devices and DRAM cells or logic devices, the art increasingly uses the creation of passive components such as capacitors or inductors as part of an integrated semiconductor device processing sequence. This integration of the creation of active and passive semiconductor components has the advantage of being cost-effective in addition to providing additional freedom in designing more complex semiconductor device functions.
As dimensions of advanced Integrated Circuit (IC) devices have continued to decrease, so also have the dimensions of conductors and interconnection elements, which connect and interconnect those integrated circuit devices. In particular, dimensions of conductor and interconnection elements which directly contact IC devices have typically decreased the greatest, thus becoming the smallest in dimension of conductor and interconnecting elements within advanced IC devices. These most narrow conductor and interconnection elements typically comprise the first conductor or interconnection level, which contacts an integrated circuit device. Most commonly, first conductor levels have been formed from aluminum metal or aluminum metal alloys. Most commonly, first interconnection levels (i.e. first conductive contact studs) are formed of tungsten. As IC device dimensions have decreased while simultaneously maintaining and increasing demands for performance of IC devices, it has become increasingly more important for conductor and interconnection elements within IC devices to exhibit a high level of conductivity while simultaneously showing limited susceptibility to degradative phenomena such as electromigration.
One of the major design considerations in creating complex semiconductor devices is the selection of the type of insulating material that is used for the creation therein of conductive or electrically active components, such as inductors or capacitors. A design parameter that has a critical influence on the performance of the created component is the dielectric constant k of the selected insulating material, whereby it is required in most applications to select a material having a low dielectric constant. For instance, embedding a conductive interconnect in an insulating material having a high dielectric constant causes an undesired increase in parasitic capacitance between the interconnect and the substrate.
As an example of the application of an insulating dielectric can be cited silicon oxide, that is grown by thermal oxidation or by chemical vapor deposition, having a dielectric constant in the order of 3.9, CVD oxide having a relative dielectric constant of about 4.6. The lowest possible and therefore the ideal dielectric constant is 1.0, this is the dielectric constant of a vacuum whereas air has a dielectric constant of slightly larger than 1.0. Dielectric constants of dielectric materials that can be used for intra-level or inter level dielectric material vary, typical values are for instance 4.1-4.5 for inorganic Plasma SiO2, 3.5 for inorganic fluorine doped SiO2 (FSG), 2.7-3.0 for Organic Polysilsequioxane (Si polymer), 2.7 for organic Bemzocyclobutene (BCB), etc.
Conventionally, semiconductor device supporting features, such as layers of conductive interconnect metal or passive components, are created in one level of insulating material on one level of deposition of this material. Design requirements and the need for increased layout flexibility indicates that it is advantageous to be able to create such supporting features without the restriction that these features are created on one level of deposition of the insulating material. The invention provides method that addresses this aspect of semiconductor device creation.
U.S. Pat. No. 6,258,688 B1 (Tsai) shows a high and low polysilicon and inductor process.
U.S. Pat. No. 6,057,202 (Chen et al.) shows an inductor process.
U.S. Pat. No. 6,008,102 (Alford et al.) shows a 3D inductor process.